The HS switched bus conveys data to the FDIU (for the DFDR), FWCs, ECAM
CP. The LS unswitched bus sends maintenance data (DMC BITE contents) for
the CFDIU.
(Ref. Fig. 010)
4. Switching of the Various Onside & Offside DMC Input Buses
_________________________________________________________ The following tables give the three kinds of buses (ARINC 429, ARINC 453 (for the W/R), RS 422) received by the three DMCs. In addition, they define which bus each DMC uses, in the normal case (N) and in the alternate case (A), i.e. when the Normal source is not available. In the column PROCESSED BY DMC No. 1 2, X means : the DMC constantly processes the corresponding bus. The failure of this bus does not cause a switching of the DMC to another source. More often, the corresponding flag(s) appears on the DUs.
1EFF : 106-149, 303-399, 1 31-68-00Page 24 1 1 Config-3 Aug 01/05 1 1 1CES 1
DMC Output Buses Figure 010
1EFF : 1 1 1CES 106-149, 303-399, 1 111 Page 2531-68-00 Config-3 Aug 01/05
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| | SPEED | | | | | | (HIGH | WIRED | | | | | SPEED,| TO DMC| PROCESSED | | | | LOW | No. | BY DMC No.| | | | SPEED)| 1 2 3 | 1 2 | | |-------------------|-------|-------|-----------|----------------------------| | ADIRU : IR BUS 1 | HS | X X | N | For CAPT : A if CAPT | | 2 | HS | X X | N | selects ATT/HDG CAPT/3 on | | 3 | HS | X X X | A A | the SWITCHING panel. | | | | | | Ditto for DMC 2. | |-------------------|-------|-------|-----------|----------------------------| | ADIRU : ADR BUS 1 | LS | X X | N | For CAPT : A if CAPT | | 2 | LS | X X | N | selects ADC INST CAPT/3 on | | 3 | LS | X X X | A A | the SWITCHING panel. | | | | | | Ditto for DMC 2. | |-------------------|-------|-------|-----------|----------------------------| | FAC 1 | HS | X X X | N A | Selection following FAC | | 2 | HS | X X X | A N | validity (healthy signal | | | | | | and bus validity) and ADC | | | | | | INST switching | |-------------------|-------|-------|-----------|----------------------------| | FMGC : A BUS 1 | HS | X X X | N A | FD (if selected) or FMA | | (FGC) 2 | HS | X X X | A N | information taken from | | | | | | onside or offside bus | | | | | | according to availability | |-------------------|-------|-------|-----------|----------------------------| | FMGC : EIS BUS 1 | HS | X X X | N A | Selection following bus | | (FMC) 2 | HS | X X X | A N | validity (healthy signal | | | | | | and bus validity) | ------------------------------------------------------------------------------
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| | SPEED | | | | | | (HIGH | WIRED | | | | | SPEED,| TO DMC| PROCESSED | | | | LOW | No. | BY DMC No.| | | | SPEED)| 1 2 3 | 1 2 | | |-------------------|-------|-------|-----------|----------------------------| | FCU 1-1 | LS | X X | X | Inside FCU, switching on | | 1-2 | LS | X X | X | processor 2 in case of | | 2-1 | LS | X X | X | failure of processor 1 | | 2-2 | LS | X X | X | | |-------------------|-------|-------|-----------|----------------------------| | VOR 1 | LS | X X X | X X | | | 2 | LS | X X X | X X | | |-------------------|-------|-------|-----------|----------------------------| | ILS 1 | LS | X X X | X X | ILS1<--> PFD-CAPT & ND-F/O | | 2 | LS | X X X | X X | ILS2<--> PFD-F/O & ND-CAPT | | | | | | in standard definition | |-------------------|-------|-------|-----------|----------------------------| | R/A 1 | LS | X X X | N A | | | 2 | LS | X X X | A N | | |-------------------|-------|-------|-----------|----------------------------| | DME 1 | LS | X X X | X X | | | 2 | LS | X X X | X X | | |-------------------|-------|-------|-----------|----------------------------| | ADF 1 | LS | X X X | X X | | | 2 | LS | X X X | X X | | ------------------------------------------------------------------------------
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| | SPEED | | | | | | (HIGH | WIRED | | | | | SPEED,| TO DMC| PROCESSED | | | | LOW | No. | BY DMC No.| | | | SPEED)| 1 2 3 | 1 2 | | |-------------------|-------|-------|-----------|----------------------------| | W/R 1-1 | ARINC | X X X | N (N) | On CAPT side : | | 1-2 | 453 | X X X | (N) N | - automatic selection | | 2-1 | (very | X X X | A (A) | 1-1/1-2 --> 2-1/2-2 for | | 2-2 | high | X X X | (A) A | DMC1 when W/R XCVR2 active | | | speed)| | | instead of W/R XCVR1 | | | | | | - automatic inhibition of | | | | | | 1-1 if FMGC 1 EIS bus | | | | | | invalid. | | | | | | Ditto on F/O side | | | | | | (with respective buses) | |-------------------|-------|-------|-----------|----------------------------| | FWC 1-1 | HS | X | X | If not valid on onside | | 1-2 | HS | X | X | bus, label is taken from | | 1-3 | HS | X | | offside bus | | 2-1 | HS | X | X | | | 2-2 | HS | X | X | | | 2-3 | HS | X | | | |-------------------|-------|-------|-----------|----------------------------| | 1-1 | RS 422| X | N | A when FWC 1-X RS422 bus | | 1-2 | RS 422| X | N | is seen faulty | | 1-3 | RS 422| X | | | | 2-1 | RS 422| X | A | | | 2-2 | RS 422| X | A | | | 2-3 | RS 422| X | | | |-------------------|-------|-------|-----------|----------------------------| | SDAC 1 | HS | X X X | X X | | | 2 | HS | X X X | X X | | ------------------------------------------------------------------------------
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