NOTE : When there is only one DU left for the ECAM display, priority
____ is given to the E/W image display. However, should any monitored parameter exceed its corresponding ADVISORY threshold, the ADV white message flashes on the lower part of the E/W image. On the ECAM CP, the key of the affected A/C system flashes in order to enable the pilot to find it easily and to consult the corresponding system image temporarily by pressing the key.
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D. Switching of the DMC Output Buses The DMCs transmit data on two ARINC 429 buses : one high speed switched bus and one low speed unswitched bus. Switched means : when a pilot sets the EIS DMC selector switch to CAPT/3 (or F/O/3), the DMC 1 (or DMC 2 respectively) sends through its output bus the data received from the DMC 3, instead of its own data.
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-68-00Page 24 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1R **ON A/C 001-049, 051-099, 101-102, 201-202, 211-299, 301-302,
The HS switched bus conveys data to the FDIU (for the DFDR), FWCs, ECAM
CP, and DMU (for AIDS). The LS unswitched bus sends maintenance data (DMC
BITE contents) for the CFDIU.
(Ref. Fig. 010)
R **ON A/C 103-105, 151-199, 203-210,
The HS switched bus conveys data to the FDIU (for the DFDR), FWCs, ECAM
CP. The LS unswitched bus sends maintenance data (DMC BITE contents) for
the CFDIU.
(Ref. Fig. 010A)
R **ON A/C 001-049, 051-099, 101-105, 151-199, 201-299, 301-302,
4. Switching of the Various Onside & Offside DMC Input Buses
_________________________________________________________ The following tables give the three kinds of buses (ARINC 429, ARINC 453 (for the W/R), RS 422) received by the three DMCs. In addition, they define which bus is used by each DMC, in the normal case
(N) and in the alternate case (A), i.e. when the Normal source is not available. In the column PROCESSED BY DMC No. 1 2, X means : the DMC is constantly processing the corresponding bus. The failure of this bus does not cause a switching of the DMC to another source. More often, the corresponding flag(s) appears on the DUs.
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DMC Output Buses
Figure 010
R 1EFF : 001-049, 051-099, 101-102, 201-202, 1 31-68-00Page 26 1211-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1
DMC Output Buses
Figure 010A
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------------------------------------------------------------------------------
| | SPEED | | | | | | (HIGH | WIRED | | | | | SPEED,| TO DMC| PROCESSED | | | | LOW | No. | BY DMC No.| | | | SPEED)| 1 2 3 | 1 2 | | |-------------------|-------|-------|-----------|----------------------------| | ADIRU : IR BUS 1 | HS | X X | N | For CAPT : A if CAPT | | 2 | HS | X X | N | selects ATT/HDG CAPT/3 on | | 3 | HS | X X X | A A | the SWITCHING panel. | | | | | | Ditto for DMC 2. | |-------------------|-------|-------|-----------|----------------------------| | ADIRU : ADR BUS 1 | LS | X X | N | For CAPT : A if CAPT | | 2 | LS | X X | N | selects ADC INST CAPT/3 on | | 3 | LS | X X X | A A | the SWITCHING panel. | | | | | | Ditto for DMC 2. | |-------------------|-------|-------|-----------|----------------------------| | FAC 1 | HS | X X X | N A | Selection following FAC | | 2 | HS | X X X | A N | validity (healthy signal | | | | | | and bus validity) and ADC | | | | | | INST switching | |-------------------|-------|-------|-----------|----------------------------| | FMGC : A BUS 1 | HS | X X X | N A | FD (if selected) or FMA | | (FGC) 2 | HS | X X X | A N | information taken from | | | | | | onside or offside bus | | | | | | according to availability | |-------------------|-------|-------|-----------|----------------------------| | FMGC : EIS BUS 1 | HS | X X X | N A | Selection following bus | | (FMC) 2 | HS | X X X | A N | validity (healthy signal | | | | | | and bus validity) | ------------------------------------------------------------------------------
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-68-00Page 28 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1 ------------------------------------------------------------------------------| | SPEED | | | | | | (HIGH | WIRED | | | | | SPEED,| TO DMC| PROCESSED | | | | LOW | No. | BY DMC No.| | | | SPEED)| 1 2 3 | 1 2 | | |-------------------|-------|-------|-----------|----------------------------| | FCU 1-1 | LS | X X | X | Inside FCU, switching on | | 1-2 | LS | X X | X | processor 2 in case of | | 2-1 | LS | X X | X | failure of processor 1 | | 2-2 | LS | X X | X | | |-------------------|-------|-------|-----------|----------------------------| | VOR 1 | LS | X X X | X X | | | 2 | LS | X X X | X X | | |-------------------|-------|-------|-----------|----------------------------| | ILS 1 | LS | X X X | X X | ILS1<--> PFD-CAPT & ND-F/O | | 2 | LS | X X X | X X | ILS2<--> PFD-F/O & ND-CAPT | | | | | | in standard definition | |-------------------|-------|-------|-----------|----------------------------| | R/A 1 | LS | X X X | N A | | | 2 | LS | X X X | A N | | |-------------------|-------|-------|-----------|----------------------------| | DME 1 | LS | X X X | X X | | | 2 | LS | X X X | X X | | |-------------------|-------|-------|-----------|----------------------------| | ADF 1 | LS | X X X | X X | | | 2 | LS | X X X | X X | | ------------------------------------------------------------------------------
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