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DMU Internal Components
Figure 007
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The I/O interface has these components:
- A I/O gate array
- Analog driver
- Analog receiver
- Three ARINC 429 transmitters
- Four ARINC 429 receivers
- One DAR transmitter.
R **ON A/C 051-099,
R A. Data Management Unit (DMU)
R (Ref. Fig. 004A, 005A, 006A, 008)
R
R The DMU is a microprocessor-controlled unit with a module for collection
R and processing of digital parameters to monitor data by various aircraft
R systems. An expanded function is the creation of various A/C condition
R reports.
R This monitoring is to derive maintenace relevant data. The internal SAR
R stores the result of specific trigger conditions. An additional function
R is the quicker access to the SAR stored data via the PCMCIA-Interface. An
R installed PCMCIA-Card is able to store the same data as the SAR.
R The DMU-functional block diagram illustrates the internal connection of
R the functional modules of the DMU.
R B. Hardware Layout of the DMU
R (Ref. Fig. 007A)
R (1) Mechanical Construction of the DMU:
R - Slot 1 power supply board assy
R - Slot 2 ARINC I/O 32IN, 8 OUT
R - Slot 3 SAR memory 2Mbytes
R - Slot 4 CPU 1 board assy, 24 ARINC IN
R - Slot 5 CPU 2 board assy, PCMCIA media interface.
R
R (2) Electrical Construction of the DMU
R The electrical construction of the DMU is divided into three
R different groups:
R - The microprocessor system
R - The ARINC interface
R - The I/O interface,
R The microprocessor system consists of these components:
R - Two Motorola 68302 microprocessors
R - Two interrupt controllers
R - one PAL address decoder
R - one clock generator
R 1EFF : 001-049, 051-099, 101-105, 1 31-36-00Page 39 1 1 Config-1 May 01/05 1 1 1CES 1R DMU Internal Components R Figure 007A
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DMU Interface R Figure 008
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R R R R R R R R R R R R R R R R R - a bus controller - 128 Kbytes EPROM for CPU 1 - 128 Kbytes EPROM for CPU 2 - 1 Mbytes Flash PROM for CPU 1 - 1 Mbytes Flash PROM for CPU 2 - 256 Kbytes RAM for CPU 1 - 256 Kbytes RAM for CPU 2 - 64 Kbytes EEPROM for CPU 1 - 1,5 Mbytes RAM for all - 2 Mbytes XMS RAM (extern) for all The I/O interface consits of these components: - An I/O gate array - Analog driver - Analog receiver - Three ARINC 429 transmitters - Four ARINC 429 receivers, - One DAR transmitter.
R **ON A/C 001-049, 051-099, 101-105,
C. Software Layout of the DMU
The DMU software is stuctured in 3 levels: - Level 1 = Boot Software - Level 2 = DMU Operational Software - Level 3 = DMU Database.
R **ON A/C 001-049, 101-105,
D. Hardware Determined Function of the DMU
(1) Circuit Board on Plug 1 (CALIN 3) Power Supply: - Internal power supply - Battery charger - Power voltages monitoring - Transients and restart circuitry - Inputs and outputs maintenace via the test connector.
(2) Circuit Board on Plug 2 (CIT32V) ARINC 429 I/O: - 32 inputs - 8 outputs - Fully programmable - HI or LO speed
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- Storage mode of data acquisition (adress=channel label SDI) or queue mode for interface dialog with periherals (Acquisition thru FIFO buffer).
(3) Circuit Board on Plug 3 (ESCARPIN - 100) Microprocessor 3: - Optional.
(4) Circuit Board on Plug 4 (ESCARPIN) Microprocessor 1: - Master in charge of acquisition I/O, reports - CPU block: 68302/20 Mhz - Local EEPROM: boot - Local flash: program and data base - Common flash: shared data base - Local non volatile RAM: standard RAM and data collection buffers - Common non volatile RAM: multiprocessor data and semaphore exchange. Shared Data collection buffers - ARINC 429: 24 inputs.
(5) Circuit Board on Plug 5 (ALINE) Microprocessor 2: - Slave in charge of DAR/SAR - CPU block: 68302/20 Mhz - DAR interface - Discrete inputs and outputs - SAR memory (2 MB).
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