Filtered Parameters - Table 9
R 1EFF : 001-049, 051-099, 101-105, 1 31-36-00Page 29 1 1 Config-1 May 01/05 1 1 1CES 1 E. Printer Word
PRINTER | DMU ------------------|------------------------------------------------------------
POLL | |
| RTS |
CTS | |
| STX |
| 1st CNTL WORD |
| 2nd CNTL WORD |> 1st block
| data for line 0 | block is
| 1st CNTL WORD | limited to
| 2nd CNTL WORD | 128 words
| data for line 1 |
| . |
| . |
| . |
| 1st CNTL WORD |
| 2nd CNTL WORD |
| data for line 1 |
| ETX |
ACK | |
| |
POLL | |
| RTS |
CTS | |
| STX |
| 1st CNTL WORD |
| 2nd CNTL WORD |
| data for line I+1 |
| . |> 2nd block
| . | block is
| . | limited to
| 1st CNTL WORD | 128 words
| 2nd CNTL WORD |
| data for line J |
| EOT |
ACK | |
The printer then polls the highest priority system.
Printer Word Exchange - Table 10
7. Component Description_____________________
R 1EFF : 001-049, 051-099, 101-105, 1 31-36-00Page 30 1 1 Config-1 May 01/05 1 1 1CES 1
R **ON A/C 001-049, 101-105,
A. Data Management Unit (DMU) (Ref. Fig. 004, 005, 006)
The DMU is a microprocessor-controlled unit with a module for collection and processing of digital parameters to monitor data by various aircraft systems. An expanded function is the creation of various A/C condition reports. This monitoring is to derive maintenace relevant data. The internal SAR stores the result of specific trigger conditions. The DMU-functional block diagram illustrates the internal connection of the functional modules of the DMU.
B. Hardware Layout of the DMU (Ref. Fig. 007)
(1)
Mechanical Construction of the DMU:
-
Slot 1 power supply board assy
-
Slot 2 ARINC I/O 32IN, 8 OUT
-
Slot 3 SPARE (for CPU 3)
-
Slot 4 CPU 1 board assy, 24 ARINC IN
-
Slot 5 CPU 2 board assy, SAR - 2Mbytes, DAR interface
(2)
Electrical Construction of of the DMU The electrical construction of the DMU is divided in four different groups:
-
The microprocessor system
-
The ARINC interface
-the I/O interface.
The microprocessor system consists of these components:
-
Two Motorola 68302 microprocessors
-
Two interrupt controllers
-
One PAL address decoder
-
One clock generator
-A bus controller
-
128 Kbytes EPROM for CPU 1
-
128 Kbytes EPROM for CPU 2
-
1 Mbytes Flash PROM for CPU 1
-
1 Mbytes Flash PROM for CPU 2
-
256 Kbytes RAM for CPU 1
-
256 Kbytes RAM for CPU 2
-
64 Kbytes EEPROM for CPU 1
-
64 Kbytes EEPROM for CPU 2
-1,5 Mbytes RAM for all
-2 Mbytes XMS RAM (extern) for all.
R 1EFF : 001-049, 101-105, 1 31-36-00Page 31 1 1 Config-1 May 01/05 1 1 1CES 1
AIDS - DMU Figure 004
R 1EFF : 1 1 1CES 001-049, 101-105, 1 111 Page 3231-36-00 Config-1 May 01/05
R AIDS - DMU
R Figure 004A
R 1EFF : 051-099, 1 31-36-00 Page 33
1 1 Config-1 May 01/05
1 1
1CES 1
DMU Internal Block Diagram
Figure 005
R 1EFF : 001-049, 101-105, 1 31-36-00Page 34 1 1 Config-1 May 01/05 1 1 1CES 1R DMU Internal Block Diagram R Figure 005A
R 1EFF : 051-099, 1 31-36-00Page 35 1 1 Config-1 May 01/05 1 1 1CES 1
DMU DITS Input Bus and Input Data Flow
Figure 006
R 1EFF : 001-049, 101-105, 1 31-36-00Page 36 1 1 Config-1 May 01/05 1 1 1CES 1R DMU DITS Input Bus and Input Data Flow R Figure 006A 中国航空网 www.aero.cn 航空翻译 www.aviation.cn 本文链接地址：A320飞机维护手册 AMM 指示/记录系统 3(19)
