-Failure information.
The BITE uses input from the same hardware devices and sensors already
used for APU control and operation. This ensures a safe and reliable
operation of the APU. When the BITE detects a failed device or an
operational fault, the ECB stores the failure in the BITE fault memory.
The BITE of the ECB operates in three modes:
-Power Up Test (PUT),
-In Operation Test (IOT),
-Self Test (SET).
-Ground Scanning
PUT
The PUT is an automatic system self-test which is initiated when the ECB
has finished its initialization and the APU speed (N) is less than 7
%rpm.
IOT
The IOT tests automatically those LRUs which have to be tested during APU
operation.
SET
The SET is similar to the PUT, but has to be called up via a CFDS menu
page.
Dependant on the faults the ECB either prevents an APU start or shuts down the APU or operates the APU with certain default operating values. The CFDS gives access to the fault data via the MCDU.
C. Not Applicable
R **ON A/C 001-003, 051-099, 401-499,
4.
Power Supply
____________
(Ref. 49-61-00).
5.
Interface
_________
A. Aircraft Digital Interface The ECB communicates to the aircraft via three seperate LOW SPEED ARINC 429 buses.
(1)
ARINC 429 Input from the CFDS The ECB uses this bus to receive specified data from the CFDS with applicable ARINC lables.
(2)
ARINC 429 Output to the CFDS
The ECB uses this bus to transmit data to the
-CFDS
-SDAC
-AIDS.
(3)
ARINC 429 Input from the ECS The ECB uses this bus to receive specific data from the ECS.
B. APU-System Interface
(Ref. 49-61-00).
6. Component Description
_____________________
A. Encoder 116KD The encoder is a four wire device. A 10 VDC signal is output from the ECB to the three resistors R1, R2, R3. They are installed and potted in a canister to avoid the effects of vibration or other mechanical forces. The canister is attached on the APU. The values chosen for these resistors correspond to a digit and each resistor reperesents a digit of the APU serial number. The ECB senses these values and thus it calculates the APU S/N.
B. Electronic Control Box (ECB) 59KD
(Ref. 49-61-00).
7. Operation/Control and Indication:
_________________________________
**ON A/C 001-003, 051-062,
The BITE of the ECB 59KD operates in three main modes:
-Power Up Test (PUT) mode,
-In Operation Test (IOT) mode,
-self test mode. The test mode in which the ECB operates is related to the step of APU operation and also which of the LRUs are examined. A list of the LRUs examined by the ECB BITE during the different test modes is shown in Table
1.
A.
Power Up Test (PUT) The BITE of the ECB 59KD automatically starts the PUT when the MASTER SW 14KD is set to ON. The BITE sends test signals to the different control system components and sensors, and makes an analysis of the replies. The ECB then makes a logic decision (with the use of the data collected) to permit or stop an APU start attempt. The ECB can also permit the APU start to continue, although some unimportant LRUs have failed; it uses alternative control values and schedules. The LRU failures are kept in the BITE fault memory. The ECB prevents an APU start until the PUT is completed. This will take approximately 3 s. If no APU is connected to the ECB, a class 1 fault "NO APU CONNECTED" will be stored in the memory but no additional faults will be stored in the ECB and no fault message will be transmitted to the CFDS. All testable LRUs will be tested, including the ECB, the flap actuator and the generator oil temperature sensor.
B.
In Operation Test (IOT) The IOT mode functions during the APU start up, operation and shutdown. The BITE of the ECB 59KD continuously monitors the APU operation limits. It makes sure that the APU operates in a pre-programmed envelope. The LRU failures are kept in the BITE fault memory. The ECB, with the ECB configuration known, and the record of LRU failures can:
-start an automatic shutdown, or,
-
continue operation with the use of alternative values for the failed LRUs, or,
-
continue operation if LRUs fail.
(1)
APU Start During an APU start, the BITE of the ECB monitors the APU performance and will stop the sequence if the APU goes out of limits (a pre-programmed envelope). The cause is kept in the BITE fault memory.
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