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时间:2011-04-01 08:39来源:蓝天飞行翻译 作者:航空
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 H. Speed Trim System
 (1)  The speed trim system controls the stabilizer trim motor to provide positive speed stability during certain low speed, high thrust flight conditions. The system is automatically engaged when the autopilot is disengaged, flaps are not up, engine speed exceeds a prescribed amount and control column limit switches are not activated.
 I. DFCS Built-In Test Equipment (BITE)
 (1)  The DFCS has three built-in maintenance features: (1)-ground maintenance Built-In Test Equipment (BITE), for on ground system checkout, (2)-continuous monitoring, for system verification, and (3)-maintenance monitoring, for inflight fault storage.
 (a)  
An extensive ground maintenance BITE capability is embedded within the DFCS. BITE can be used for line maintenance fault isolation in less than 5 minutes, and overnight maintenance actions when extensive engineering investigating or trouble shooting is required. A land mode verification feature is available for autoland reinstatement after system LRU replacement. BITE is primarily intended for use by the line mechanic and utilizes software and circuitry which is not flight critical (i.e., does not influence in-flight system operation).

 (b)  
The continuous monitor provides on-line monitoring to determine the health of the FCC's and system input/output operation. When a fault is detected, a fault reaction occurs: either a mode dropout, an autopilot disconnect, or F/D bars bias out of view. In the DFCS, this monitoring covers the computation, the RAM/ROM memories and partly the power supplies. Continuous system monitoring is also provided to detect failurs on incoming digital signals, and in the actuator position feedback loops.


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737-300/400/500MAINTENANCE MANUAL
 (c)  The maintenance monitor records the causes of DFCS related cockpit effects. These include on-line faults detected by the continuous monitor and system failures that cause an autopilot disconnect, prevent autopilot engagement, cause a F/D bar out-of-view bias, or cause mach trim/speed trim failures. The system records the cockpit effect, the LRU diagnostic, the monitor that tripped, and if the fault is repeated in the flight segment. This data is retreived on the ground through ground maintenance BITE by selecting INFLIGHT faults.
 2.  Flight Control Computer (FCC)_____________________________
 A.  Two flight control computers (FCC) designated as A and B are mounted on the E1-3 shelf in the electrical and electronics equipment bay. The units are retained in the rack by cam-loc handles located on the front of the unit which engage adjustable rack-mounted swivel bolts. The flight control computers are standard 1 ATR-long boxes. Electrical connections to the units are provided by four DPX2 connectors located on the rear of the unit which mate with rack-mounted DPX2 connectors. Three capped test connectors and a cooling fan are located on the front panel of the flight control computers.
 B.  The FCC contains keyed plug-in printed circuit cards which are installed vertically within the unit. The cards have built in lever assist handles for ease of removal. The unit power supply consists of plug-in cards located across the rear of the unit. The electronic circuitry on the boards are latest state-of-the-art design with solid state micro-electronics used extensively.
 C.  The FCC interfaces with analog and digital data signals. The mode computation is performed by the digital computer. Analog to digital (A/D) and digital to analog (D/A) converters within the computer provide system compatability. The computer is designed to interface with ARINC 429 digital data.
 D.  Airplane compatibility is determined by the three option pins in the FCC. These pins shall be used to compare against the allowable combination of FCC and airplane. The failure to pass the compatibility check shall result in the computer failing the power up test. The airplane compatibility is displayed on the CDU in the standard option pins table (Ref. 22-11-00/501, Digital Flight Control System - Adjustment/Test).
 E.  Operation of the FCC (Fig. 2) is centered around two digital processors. The CPU 1 processor performs most mode logic and control while CPU 2 does parallel computations for dual-channel autoland functions and provides the pitch inner loop and limiting functions. Computations are split between the two processors to preclude one processor failure from causing a simultaneous roll and pitch Autopilot hardover. Control and logic calculations are shared between the processors for critical applications. All signals to and from the FCC and data transferred between the processors are controlled by a direct memory access controller.
 
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