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115V AC28V DC
CU FUNCTIONSDIGITAL DATA TO CUMASTER CLOCK DIGITAL DATA
REGULATED 16V DC TO TRANSMITTER
INDICATOR DC
CU & MU FAULT
DATA KEYLINE10 MHzFREQUENCY
PROGRAMMING 1 MHzCHANNEL
0.1 MHzSELECTOR
MHz0.01IN/OUTFREQ SEL COM
IN/OUTON/OFF VOICE GO-AHEADAPU 95%
MANAGEMENT UNIT (E2-1)
IDU (P8)
OOOI AND REG PROGRAM PINS
E2-1 SHELF WIRING
MISC SWITCHING MODULE (E3-2)
LANDING GEAR LOGIC SHELF (E11)
APU CONTROL UNIT (E3-3) ANT AURAL
REMOTE ELECTRONIC WARNING
UNIT (E2-1)MODULE(STA 200WL 209.30RBL 9.06)
VHF NO. 3 TRANSCEIVER(E2-1)
ACARS Block Diagram
Figure 3
G38258
A 737-300/400/500MAINTENANCE MANUAL
G38259
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(2)
(3)
(4)
A 737-300/400/500MAINTENANCE MANUAL
(b)
Under normal conditions the main, IDU, and standby voltages are derived from the 115v ac power source, no current being drawn from the 28v dc battery bus. When 115v ac power is removed from the MU, the main and IDU output voltages go to zero while the standby output voltages, being derived from the 28v dc source, remain. The standby output voltages are used to maintain data stored in memory.
MU Microprocessor (.P)
(a)
The .P is a single-chip, 16-bit .P. Addresses for instructions are supplied to the address bus (A00-A14) by the .P's memory address register. Instructions read from memory are loaded into the .P's instruction register via the data bus (D00-D15). Subsequent operands are read from and written into memory in the same manner using register files in memory, the .P's source data register, status register, and arithmetic logic unit (ALU).
(b)
The .P uses a direct command-driven I/O interface designated as the CRU (Communications Register Unit). The .P employs three dedicated I/O pins (CRU IN, CRU OUT, and CRU CLK) and 12 bits (A03-A14) of the address bus at the interface to the CRU system. The .P instructions that drive the CRU interface can set, reset, or test any bit in the CRU array or move data between memory and CRU data fields.
(c)
A CRU CLK signal indicates that external interface logic should sample the output data on CRU OUT or decode external instructions.
(d)
The CRU IN line receives input data from external interface
logic.Programmable System Interface
(a)
The programmable system interface circuit interfaces with the .P through the CRU and interrupt control lines. The interrupt section prioritizes and encodes the highest priority active interrupt and outputs this code on the IC0-IC3 code lines along with an active INTREQ signal.
Clock Interface
(a)
The clock interface consists of a 48 MHz quartz crystal, oscillator, two divide by four counters, and a flip flop. The flip flop is used to reset the .P and is controlled by the on logic signal, from the power supply, and phase 3 clock signal.
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A 737-300/400/500MAINTENANCE MANUAL
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