The discrete outputs and the relays are managed by the main
microprocessor.
Darlington transistor units permit to translate the 5V TTL levels
into standard GROUND - OPEN outputs.
Other Darlington transistor units drive the relay coils.
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(5) CSP - MSP boards
These boards are identical.
They include:
-a 16-bit microprocessor (68000)
- one ARINC 429 output (for transmission of information between ELAC1 and ELAC2) These boards operate as co-processor associated to CPU-MPU boards.
5. Operation
_________
The ELAC has two independent computation units.
(Ref. Fig. 016)
Each unit performs:
-an acquisition and validation of the signals required for its
computations.
-a computation of the different laws which generate the control surface deflection order (Ref. 27-90).
-
slaving for the generation of the command current
. in COM for surface slaving
. in MON for monitoring of the orders generated in COM.
A.
Monitoring of Peripherals (IMP VAL) The acquisition and monitoring principles of the signals at the input permit:
-
a safe operation due to failure detections
-
a maximum availability due to the reconfigurations further to these failures.
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ELAC - Functional Diagram Figure 016
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(1) Accelerometer
(a)
Architecture
(Ref. Fig. 017)
Each computer unit receives the values of the load factor
measured by 2 accelerometers and the IRS.
(b)
Monitoring Monitoring of the difference between the 2 accelerometers received and elimination of the erroneous accelerometers through comparison of the load factor value from the IRS. In normal operation, the measured load factor value which is used in the pitch normal law is the half-sum of the two accelerometer signals.
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Accelerometer Architecture Figure 017
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(2) ADIRS
(a) Architecture
R (Ref. Fig. 018) Each computer unit receives the 3 ADIRUs:
-2 ADIRUs are directly received by the unit
-the 3rd ADIRU comes from the associated unit
(b) Monitoring Each unit performs the monitorings below:
-parity check
-refresh rate
-status matrix check
-monitoring of the 3 alpha probes before takeoff
-comparison between signals from the 3 ADIRUs.
In normal operation, the values used in the law computation are:
-
for the IRUs, the half-sum of the two values from the two IRUs that each unit directly receives.
-
for the ADRs, the half-sum of the two values from the two ADR 1 and 2.
After one IRU or ADR failure, the value used for the law computation is the half-sum of the two remaining IRUs or ADRs. Each unit continues to perform the comparison between the remaining values.
The ELACs take into account the IRS mode (NAV mode/ATT mode)
-While at least one IRU is seen in NAV mode, an IRU seen in ATT mode is set to the failure state.
-When there is no IRU in NAV mode, if at least one IRU is seen in ATT mode, only one of the IRUs in ATT mode is used by the ELACs. Consequently the ELACs work in alternate law.
(3) Side stick order transducers
(a) Architecture
R (Ref. Fig. 019) Each unit receives two signals which give the Captain side stick position in pitch. - one signal comes from the potentiometer directly received by
the unit.
-the other signal comes from the potentiometer received by the
associated unit.
REMARK:
R R ADIRS Architecture Figure 018
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R Side Stick Order Transducer Figure 019
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An identical architecture is found on the potentiometers which give:
-
the position of the CAPT side stick in roll,
-
the position of the F/O side stick in pitch,
-
the position of the F/O side stick in roll.
(b) Monitorings performed in the ELAC
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