1EFF : 106-149, 303-399, 1 31-63-00Page 67 1 1 Config-3 Aug 01/05 1 1 1CES 1 7 Memory block
_ Memory of the SG is divided in 4 parts:
a 6K 16 bit-words in EEPROM for the monitor program and the
_
alphanumerics,
b 10K 16 bit-words in EEPROM for the PFD, ENGINE, and part of
_
the ND programs.
c 15K 16 bit-words in RAM for current drawing program and
_
data divided in:
-
2 pages of 1K words each for rapidly refreshed data
-
2 pages of 5K words each for slowly refreshed data
-1 non paginated 3K for feedback data.
d 1K 16 bit-word, located on a 1K word address field, for DUA
_ (DU anomaly). At any time, one page is used by the SG to build the current image while the other page receives via the serial link the necessary data for the next image. The EEPROMs will be programmed via the DSDL line. This shall take place only at the electrical power on setting (DMC + DU), and only if the program stored in the EEPROM does not match that which corresponds to the DMC software. There is no specific circuit on the SG to program the EEPROM "in situ". The RAMs are protected against short power interrupt (at least 3 seconds).
NOTE : The alphanumerics field contains the description of
____ standard alphanumerics (available in 4 sizes) on one hand, and of special drawing characters on the other hand. The sizes are : 3, 3.5, 4 and 5 mm.
1EFF : 106-149, 303-399, 1 31-63-00Page 68 1 1 Config-3 Aug 01/05 1 1 1CES 1 8 Inputs/outputs controller
_ The I/O controller provides the timing for the SG system. It controls all the memory accesses and allows a shared memory access between the processor and the serial link interface.
9 Serial link controller : SDL
_
This function includes:
-
a Transmitter/Receiver circuit which performs the Serial/Parallel conversion, based on the Harris device HS 3282
-
a LSI circuit whose function is to interface the serial link with the memory. It handles the direct memory access and generates the control signals according to the labels sent by the DMC
-
a line driver circuit whose function is to interface the HS 3282 and the DSDL feedback line.
10 Clock generator
__ The LSI circuit generates all the necessary clocks for the SG. The clock reference is a 16MHz oscillator, which must be matched with the WXR clock of the DMC.
11 WXR link receiver
__ (Ref. Fig. 023)
a WXR link decoder
_
The functions of this circuit are:
-
To receive the color bits and clock signals
-
To extract the frame synchro signal
-
To reset the FIFO memory and to enable the writing
-
To trigger the LSI symbol generator.
b FIFO memory
_ The size of the FIFO memory (64 x 3) is sufficient to take care of the slight frequency difference between the SG oscillator and the DMC WXR oscillator.
1EFF : 106-149, 303-399, 1 31-63-00Page 69 1 1 Config-3 Aug 01/05 1 1 1CES 1
WXR Link Receiver - Block Diagram
Figure 023
1EFF : 106-149, 303-399, 1 31-63-00Page 70 1 1 Config-3 Aug 01/05 1 1 1CES 1
12 Safety function
__ a SG self test
_ The SG is able to be self tested because its digital outputs X, Y, blanking and color are connected via a test register on the SG bus.
b Watch dog
_ A watching circuit controls the activity of SG LSI, and of the DSDL link. It is retriggered by the INIT signal which is supplied by the SG after reception of status word by the DSDL. When the watch dog falls, then the DSDL receiver is re-initialized one time.
c Short power interrupt detection : SPID
_ Power interrupts shorter than 2 ms will not induce any change of the DU state. Power interrupts less than 3 seconds will not destroy the program RAMs content, but MASK RAMs will need reloading. In this case, a short power interrupt signal will be generated. More than 3 seconds power interrupts can destroy all RAMs content. A long power interrupt signal will then be provided.
d DU temperature
_ Two temperature levels are detected:
-
The lowest one generates an alarm
-
The second one cuts off the DU.
e DU anomaly
_ This signal results from a failure considered as possibly dangerous for the CRT. The failures are:
-plus or minus 5V, plus or minus 15V, + 100V, - 170V trouble detection
-Cathode amplifiers over-load detection
-Beam minimum velocity monitoring
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