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Main memory The main memory consists of four 16K x 4 bit dynamic RAMs (only 16K x 3 bit used) ; it thus has a total storage capacity of 64K x 4 bit (only 64K x 3 bit used). All four RAMs are presented with identical data from the beam buffer and have identical addresses at their address-inputs via the MAIN-MEMORY-ADDRESS-BUS. The selection of a particular RAM for the write-operation is, however, done by the signals W1* to W4* from the main memory control logic : whereas during the read-operation, all four RAMs are read simultaneously. The area on the ND (navigation display), where the WXR map is to be drawn, consists of a 256 x 256 grid point array ; each point being defined by an X- and Y- coordinate. The contents of the main memory are analogous to this grid, where each grid point is a memory location. The main memory write logic (X- and Y-address counters) determines the location of each BIN in the main memory during the write-operation. In order to do this, it delivers row-addresses and column-addresses via the MAIN-MEMORY-BUS. When one of the signals W1* to W4* goes to LOW, a BIN is written in a particular RAM. The X- and Y-address counters in this logic are activated by the X/Y incrementation logic via the main memory control logic. The main memory read logic (X- and Y-address counters) provides the row-addresses and column-addresses via the MAIN-MEMORY-ADDRESS-BUS during the read-operation in the main memory. As all RAMs are addressed and enabled simultaneously, 4 BINs (12 bits) are thus read out from the main memory and transmitted through the MAIN-MEMORY-DATA-BUS. Reading out of the main memory is executed using the meander-scan techniques. The X-address counters in this logic are thus conditioned for up-counting only, whereas the Y-address counters are conditioned for up- and down-counting alternately. There are two comparators - X and Y. The Y-comparator compares the position of the Y-address counter with the upper and lower limits of a writing mask fixed by the DPU2 (ND) board - ENDP.Y and START.Y. (Ref. Fig. 015)
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Writing Mask
Figure 015
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On reaching these limits, the Y-address counter begins its down- or up-count accordingly. The X-comparator compares the position of the X-address counter with the extreme-right limit of the writing-mask (ENDP.X). When these two parameters match, the X-comparator activates the signal X LIMIT*, which, in turn, asserts signal END OF WXR* in order to inform the DPU2 (ND) board that a complete beam has been read out of the main memory i.e. the beam has been simultaneously drawn on the ND. The 800 beams, which are received and processed by the WXR board every 4 s. to draw a WXR map on the ND, do not necessarily contain all the information for a complete picture. This is especially true, as the beams diverge at greater ranges. In order to provide color information to all BINs from which the WXR map is formed, a "slave beam is generated immediately after each master beam. (Ref. Fig. 016) In order to achieve this, the beam buffer is read twice. By the first read out, the BIN information of a beam is read out, as already explained, from the beam buffer (the BIN information is, thereby, not erased) and written into the main memory, the addresses of which are calculated by the main memory write logic from the COMP. ANGLE (calculated on the DPU2 (ND) board) of the main beam ; by the second read out, the same BIN information is read out once again from the beam buffer and written into the main memory under new addresses. These addresses are calculated by the main memory write logic from the same COMP. ANGLE plus Delta x and Delta y respectively from the X/Y incrementation logics ; Delta x and Delta y being fixed values delivered under control of main memory control logic. This way, each time a slave beam is written into the main memory immediately after the master beam. Correspondingly, the master beam is read out from the main memory followed by the slave beam. (Ref. Fig. 017)
X/Y incrementation logic The scan angle of the beam, contained in control word 4 in the input word, is added to the drift angle on the DPU2 (ND) board and the result - COMP. ANGLE - is fed back to the WXR board. This angle is in polar coordinates and the task of this logic is to convert the polar coordinates to cartesian coordinates. It consists of sin/cos PROMs, an adder and registers where the conversion takes place. It activates the main memory write logic (X- and Y-address counters) via the main memory control logic in order to generate the required addresses for the main memory during the write-operation
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Master Beam and Slave Beam
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