(b) DMC operation The DMC can be divided into four basic sections:
-data acquisition
-PFD channel
-ND channel
-ECAM channel.
(Ref. Fig. 005)
The data acquisition section enables the DMC to handle all input
and output signals from/to the other avionic systems in the
aircraft.
The I/O interface 1 to 3 boards and the WXR (weather radar) board
in the unit are responsible for accomplishing this task. The
hardware contents of the three I/O interface boards are almost
identical ; they differ, however, in their software contents.
(Ref. Fig. 006)
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EIS Configuration
Figure 004
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DMC - Data Flow
Figure 005
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DMC - Block Diagram
Figure 006
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 11/12 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES The data acquisition section can handle 60 discrete inputs, 54 ARINC 429 inputs, 4 WXR channels, 3 RS 422 data link inputs and 6 RS 232C data link inputs as well as 12 discrete outputs and 3 ARINC 429 outputs. The discrete input signals, which define system-commands, are received by the I/O interface boards, and each signal is transformed into 2 x 16-bit words. These words are then routed to the COMMON RAM (located on the DPU 1 (PFD) board), where they are stored in their appropriate locations for use by the DPU boards. The ARINC 429 input (high or low speed) signals, which represent navigational information, are also received by the I/O interface boards and are checked for validity and if valid, relabelled and stored in the COMMON RAM in their appropriate locations for use by the DPU boards. The RS 422 data link inputs, which represent texts/ messages, etc. generated by the FWC and to be displayed on the ECAM DU, are received serially by the I/O interface boards, converted into parallel bits and stored in the COMMON RAM for use by the DPU 3 (ECAM) board. The RS 232C data the COMMON RAM for use by the DPU 3 (ECAM) board. The RS 232C data link inputs (one each to the three I/O interface boards and the three DPU boards) are used for maintenance purposes only. The discrete output signals generated in the DMC and which represent validity signals for each channel (PFD, ND, ECAM), etc. as well as ARINC 429 output signals (2 low speed and 1 high speed) also generated in the DMC are fetched from the COMMON RAM under control of a DPU board and routed to external avionics systems via the I/O interface board. Four input channels as per ARINC 453 specifications feed WXR data from the weather radar transceiver to the WXR board; the WXR data format conforms with the ARINC 708 specification.The data is processed on this board, under the control of the DPU 2 (ND) to draw a color WXR map on the ND, which shows the weather conditions in front of the aircraft. The main function of each of the three independent channels -PFD, ND and ECAM - is to process the relevant input signals received by the data acquisition section and prepare data, which can be used by the DUs to draw the required symbols or pictures simultaneously. The processors on the boards DPU1 (PFD), DPU2 (ND) and DPU3 (ECAM) perform this function. All three boards are almost identical in hardware contents (except for the DPU1 (PFD), which contains the COMMON RAM, the BITE memory and the bus arbiter contains the COMMON RAM, the BITE memory and the bus arbiter additionally); they differ, however, in the software implemented on.
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-63-00Page 13 1201-299, 301-302, 1Config-1 May 01/05 1 1 1CES 1 The other functions of the processors on the DPU boards are :
-process status information fetched from the COMMON RAM
-react to various interrupts
-provide the frame time for the stroke picture or for the WXR picture (DPU2 (ND) only) on the respective DU
-control the digital output link to the DU
-run test routines
-generate maintenance information
-control WRX beam information (DPU2 (ND) only). To achieve all these functions, a powerfull software program and data handling is implemented in each DPU.Changes in the software for a DPU can be executed very easily - without the need of removing or dismantling the entire unit. The relevant memory module, which contains the whole software can be effortlessly pulled out of the dog-house on the unit in order to execute the changes. data communication between the I/O interface boards/WXR board and the DPU boards takes place via a COMMON BUS. It provides parallel high speed data transfer, without disturbing the internal activities on the individual board. Access to the COMMON BUS takes place via bus couplers (master or slave) and bus requesters on each board and as per priority rules. A board containing a bus master also has a bus requester, through which the board can claim access to the bus. A board containing a bus slave (WXR board) can only respond to a data transfer operation claimed by another board with a bus master. Each board (I/O or DPU) can send an independent bus-request (BR*)signal to the bus arbiter (located on the DPU1 (PFD) board). The bus arbiter grants this request with a fairness protocol and sends a corresponding bus-grant (BG IN*) signal to the particular board. The board can now use the COMMON BUS (signal busy* is asserted). The power supply module, operating on 115v/400Hz aircraaft supply voltage and controlled by the signal POWER DOWN, supplies all internal voltages in the unit.
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