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DPU Board - Block Diagram
Figure 007
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The general function of all three boards is identical. Each board
can operate independently as it contains its own CPU and memory.
The design of the board is based on the MC 68020 (CPU) concept,
which enables the use of a powerful instruction set. Its RAM
consists of the local RAM and the COMMON RAM (located on the DPU1
(PFD) board).
The access to the COMMON RAM, hoxever, is via the COMMON BUS and
hence the priority rules apply.
Its whole ROM is located on the OBRM. This means that the
complete software of each DPU is located on the OBRM.
The main tasks of each DPU board are:
-data processing, which includes scaling, filtering and execution of mathematical and logical functions
-control of the DUs i.e. preparation of their input data, basic timing as well as start-, verify- and switching operations
-execution of a part of the BITE (built-in test equipment) and fault isolation. The BITE memory is located on the DPU1 (PFD) board and can be accessed via the COMMON BUS.
The DPU board can be sub-divided into the following main functional blocks:
-central processing unit (CPU)
-local RAM and system EPROM
-watch dog timer, address decoder and interrupt logic
-bus requester and bus couplers
-COMMON BUS time out control
-MFPI
-MFPII
-DSDL control logic
-COMMON RAM, BITE memory and bus arbiter Data communication between individual functional blocks (excepting COMMON RAM and BITE memory) on each board is carried out by the LOCAL-DATA-BUS (32 bit, bidirectional, three state), the LOCAL-ADDRESS-BUS (32 bit, uni-directional, three state) and the LOCAL-CONTROL-BUS (comprising various control signals). For the COMMON RAM and BITE memory, a separate MEMORY-BUS is provided. This bus consists of a MEMORY-DATA BUS.
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Central processing unit (CPU)
The CPU is a 32-bit microprocessor from the MC68020 family. It
is always in one of the following three processing states:
-normal processing state, which is associated with instruction execution. In this state, the CPU fetches instructions/operands from its own system EPROM or from the COMMON RAM, processes them and stores the final result back in the COMMON RAM
-execution processing state, which is associated with interrupts, trap instructions, tracing and other exceptional conditions. In this case, a vector number, which is fetched from the system EPROM, is fed to the CPU via the LOCAL-DATA-BUS. The vector number is processed in the CPU and relevant addresses are sent to fetch the necessary instruction from the system EPROM. This instruction is executed by the CPU in order to carry out the necessary operation
-halted processing state, which is an indication of a catastrophic hardware failure. For example, if during the exception processing of a bus-error another bus-error occurs, the CPU assumes that the system is unusable and halts.
Local RAM and system EPROM When the CPU is in one of its three processing states, it requires intermediate storing facility for data/results. This is provided by the 32 K x 16 bit local RAM. It is addressed by the LOCAL-ADDRESS-BUS and data transfer takes place via the LOCAL-DATA-BUS. It is enabled by an address decoder and the read/write signals are provided by the CPU via the R/W logic. The local RAM has a special power supply line (+5 V PROT.). This provides continuous power to the local RAM even during a short-power-interrupt condition. This same line provides power to the COMMON RAM (on DPU1 (PFD) board) also. The system EPROM consists of program EPROMs and data EPROMs. The program EPROMs contain instructions required by the CPU to execute the operational program. They also contain a test library and a monitoring program for maintenance purposes, which monitor the system hardware, depending on the information received via the RS 232 serial interface. The data EPROMs contain data required by the CPU while executing the operational program. Those program EPROMs and data EPROMs, which contain the operational software, are located in the OBRM in the dog-house mounted on the front side of the unit. Those program EPROMs and data EPROMs are located on the OBRM which consists of a 128K x 32 bit EPROM bank.
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