c
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d
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Address decoder and DTACK generator
The addresses generated by the CPU are decoded by the
address decoder in order to deliver the required
enable-signals on this board.
The DTACK generator asserts the signal DTACK* in order to
inform the CPU that the CPU-DATA-BUS is being used for a
data transfer.
Interrupt logic
The interrupt logic has two functions:
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initiate an interrupt in the CPU operation on the I/O interface board
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initiate an interrupt in the CPU operation on the DPU
board. The two interrupt requests, which can claim an interrupt in the CPU operation on the I/O interface board are IRQ5* (MFP) and IRQ4* (ACIA) from the RS232 and RS422 interfaces respectively (in the serial interface logic). Their priority-level is encoded by the interrupt logic via three interrupt-priority-level signals IPL0* - IPL2* sent to the CPU. When the CPU acknowledges an interrupt-request, it asserts its function-code-outputs FC0 - FC2 and ADDRESS-STROBE signal AS* accordingly. The interrupt logic then activates either interrupt-acknowledge-signal IACK5* (MFP) or IACK4* (ACIA), which informs the RS232 or RS422 interface that an interrupt has been granted. When data from the FMGC or FWC is received by an I/O interface board, its CPU can initiate an interrupt cycle on the DPU board. In such a case, the CPU on the I/O interface board sends relevant addresses through its CPU-ADDRESS-BUS in order to activate signals CE INT1* or CE INT2* via the address decoder. These signals are transmitted via the interrupt logic as signals IRQ1* (FWC) or IRQ2* (FMGC) to the relevant DPU board to claim an interrupt in its CPU operation.
NOTE : IRQ1* (FWC) is generated on I/O interface 2 board
____ only and is transmitted to DPU2 (ND) board. IRQ2* can be generated on all three interface boards and sent to DPU3 (ECAM) board.
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e Watchdog timer and reset logic
_ The watchdog timer continuously monitors the trigger-watch-dog-flag TRW* from the ARINC control register (in ARINC I/O interface logic) at intervals determined by a clock from the clock generator. In case the flag TRW* remains inactive for a period longer than 350 ms (which happens if an error occurs during the normal processing state of the CPU), the watchdog timer generates a watchdog-reset (WDR*) signal. This resets the CPU via the RESET logic. When the unit is powered on or when the signal WDR* is activated by the watchdog timer, the reset logic resets the CPU.
f Clock generator
_ The clock generator consists of a quartz oscillator and two frequency dividers. The quartz oscillator generates a 20 MHz clock and the frequency dividers divide this clock to output various derivative clocks, which are required on this board.
Discrete I/O interface logic
Five functional groups are discussed under this heading:
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discrete input interface
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discrete output interface
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discrete wrap around test logic
-DMC invalid relay
-discrete decoder.
a Discrete input interface
_ This interface, made up of the discrete input hybrid modules and the discrete input latches, can handle a total of 20 discrete inputs (type OPEN/GND). Under the control of the CPU, the inputs are routed through the I/O-DATA-BUS, the I/O data bus coupler and the CPU-DATA-BUS to the COMMON RAM (on the DPU1 (PFD) board) for storage until further use. The CPU activates TEST MODE and TEST HI/LO via the MFP on the board in order to test the hybrid modules and the latches in this interface.
b Discrete output interface
_ This interface, made up of the discrete output module and the discrete output latch, can handle 4 discrete outputs. These outputs are fetched from the COMMON RAM, under the control of the CPU, and routed through this interface to external peripherals.
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c_ Discrete wrap around test logic
This logic provides a wrap-around-test facility for the
discrete I/O interface logic. The wrap-around loop is
formed by the discrete output interface, a wrap around
hybrid module and a wrap around latch. During the test, the
CPU transmits four bits through the CPU-DATA-BUS and
through this wrap-around-loop and then executes a
status-check.
d DMC invalid relay
_ This relay is mounted on the I/O interface 3 board only. When the DMC is switched on, it executes a short self-test cycle, during which the bit D01 at the output of the discrete output module is LOW. The DMC invalid relay is thereby energized and signal DMC-INVALID is OPEN : an indication that the DMC is not accessible for operation during this time. After the self-test cycle, bit D01 goes to HIGH and remains HIGH during the normal operation of the DMC. This de-energizes the relay and signal DMC-INVALID is held continuously at LOW. In the case of an abnormal condition in the DMC, bit D01 is again set to LOW, causing the signal DMC-INVALID to become OPEN.
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