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ARINC interface modules
-
ARINC decoder
-control and status registers
-ARINC latches.
1EFF : 106-149, 303-399, 1 31-63-00Page 30 1 1 Config-3 Aug 01/05 1 1 1CES 1
a
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b
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c
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d
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ARINC interface modules There are nine ARINC interface modules on each I/O interface board. Each interface module contains two receivers and one transmitter, all three operating independently. The function of the receiver is to receive serial data as per ARINC 429 specification via an input channel, convert it into 16-bit words and transmit these through the I/O-DATA-BUS, I/O data bus coupler and the CPU-DATA-BUS for relabelling purpose. The function of the transmitter is to receive 16-bit words through the CPU-DATA-BUS and I/O-DATA-BUS, convert them to serial bits and transmit these via the ARINC output driver to external devices. Each I/O interface board can thus handle a maximum of 18 inputs (6 high-speed and 12 low-speed) and 9 outputs (only 1 output is, however, used).
ARINC decoder This decoder decodes the addresses on the CPU-ADDRESS-BUS in order to deliver the enable- and clock-signals for the ARINC I/O interface logic.
Control and status registers The CPU uses the control register to activate definite signals by setting certain bits on the CPU-DATA-BUS. It can thus:
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enable the transmitter section in the ARINC interface module
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enable the ARINC output driver
-perform a general reset for certain sections of the discrete-, ARINC- and serial- I/O interface logic via signal RES I/O*
-trigger the watchdog timer via signal TRW*.
The status register feeds the status-information of
definite signals from the control register back to the CPU
for validity checks.
ARINC latches These latches inform the CPU about the status of the receiver- and transmitter-sections inside the ARINC interface modules via definite signals.
1EFF : 106-149, 303-399, 1 31-63-00Page 31 1 1 Config-3 Aug 01/05 1 1 1CES 1 4 Serial interface logic
_ There are two serial interfaces on each I/O interface board :
-RS422 interface
-RS232 interface.
a RS422 interface
_ This interface receives serial-data from an external device
i.e. the , converts this data to 8-bit parallel data and loads it on the CPU-DATA-BUS for eventual storage in the COMMON RAM (on the DPU1 (PFD) in the COMMON RAM (on the DPU1 (PFD) board). It consists of a line receiver and an ACIA (asynchronous communications interface adapter). The line receiver renders the serial-data-input TTL compatible and feeds it to the ACIA, which in turn is responsible for the actual serial-to-parallel conversion.
b RS232 interface
_ This interface is used for maintenance purposes and provides a serial communication with an external device
(e.g. debugger). It consists of a MFP (multi-function
peripheral) and two line drivers.
The MFP which has more functions than those described
above, is an integrated module consisting of the following
functional groups :
-general purpose I/O port (GPIP)
-interrupt controller
-timers A, B and C, D
-UART.
The CPU on the board can communicate with any of these
functional groups via the CPU-bus-lines (also in the MFP).
The GPIP handles two inputs (from the power supply module)
and two outputs (to the discrete I/O interface logic). The
power supply module uses the GPIP for two purposes :
firstly it informs the CPU on the board about the status of
the signal SPID and secondly, it requests an interrupt in
the CPU operation with signal POWER LOW.
The CPU uses the GPIP for only one purpose : it tests the
discrete input interface (in the discrete I/O interface
logic) with signals TEST MODE and TEST HI/LO.
1EFF : 106-149, 303-399, 1 31-63-00Page 32 1 1 Config-3 Aug 01/05 1 1 1CES 1 The interrupt controller handles interrupt-requests for an interrupt in the CPU operation received via the GPIP as well as those generated internally in the MFP by the UART. It sets priority-levels for these requests and sends signal IRQ5* (MFP) to the interrupt logic. When the request is granted by the CPU, it receives the signal IACK5* (MFP). The timers A and B are cascaded and operate as a real time counter, whereas the timers C and D provide the baud-rate clocks for the ACIA in the serial interface logic and the UART in this MFP. The UART (universal asynchronous receiver transmitter) in the MFP, as already explained, provides asynchronous serial communication with an external device (e.g. debugger) via the line drivers during maintenance operations. To accomplish this task, the UART operates in the receiver or in the transmitter mode. 中国航空网 www.aero.cn 航空翻译 www.aviation.cn 本文链接地址：A320飞机维护手册 AMM 指示/记录系统 7(147)
