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the CN201 connector goes through IC212 (+24V voltage regulator) and
becomes a source voltage for the D202 bias.
In overall, the PD1 and PD2 outputs become H to decrease the VCO
frequency if the VCO frequency is higher than the target value, and
become L to increase the VCO frequency if the VCO frequency is lower
than the target.
The divisor N for Fin is changed to get the desired target VCO
frequency. The divisor N is given as follows:
N = 8 (32M + S)
where M is the divisor (32 to 1023) that the main counter gives and
S is the divisor (0 to 31) that the slow counter gives. The
possible range of N is from 8192 to 262136. That is, the target VCO
frequency is selectable from 32 MHz to 1023.96875 MHz. The A1 card
sets the main-counter divisor M and slow-counter divisor S through
the DT (data) and CK (clock) lines as shown in Figure 6.
DT
CK
1 2 3 4 M M M M M M M M M M M S S S S S
BS MAIN COUNTER DIVISOR SLOW COUNTER DIVISOR
NOTE: The CK signal is at pin 4 of IC204. The CK signal at the
CN201 connector is an inverted form of the above. Q202 works
as a signal inverter.
PROGRAMMABLE FREQUENCY DIVIDER SETTING
Figure 6
The first 4 bits of the data are the band switch data for on-off
control of IC204 pin 14, 13, 12 and 11 outputs. There are no
connections to these output pins. The subsequent 10 bits are the
main counter divisor data in binary notation with the bit sequence
from the MSB to LSB. The last 5 bits are the slow counter divisor
data in binary notation with the bit sequence from the MSB to LSB.
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Matsushita Avionics Systems Corporation
COMPONENT MAINTENANCE MANUAL
PART NUMBER RD-AA5002 SERIES
23-32-47
These 19 bits are shifted into the 19-bit shift register in IC204 by
the positive-going edge of the clock signal. The DT line is kept L
in the vicinity of the negative-going edge. The DT line is made H
after the last bit. With the DT line H, the negative-going edge of
the clock signal causes the contents of the shift register to be
transferred to 19-bit data latch.
With pin 1 (test input) grounded, IC204 pin 20 gives a lock detect
output (LD). This output is L when the VCO frequency is locked to
the target frequency. The A1 card uses this output for control and
monitoring of the A2 card.
(5) Final Mixer
DBM202 mixes the 481.75 MHz RF video signal from FL210 with the VCO
output from IC211 (RF amplifier). The VCO output frequency is
changed to set the difference between the mixer input frequencies to
the necessary value. For example, if a final RF video frequency of
151.25 MHz is necessary, the VCO frequency will be set to 633 MHz.
For a final RF video frequency of 283.25 MHz, the VCO frequency will
be set to 765 MHz.
The RF video output becomes an upper sideband AM signal after
DBM202. VR202 is installed to adjust the level of the final RF
video output. VR202 changes the forward bias voltage of D203 thru
D205 (PIN diodes) to control the RF output level. The final RF
video output goes through FL211 (300-MHz lowpass filter) and IC210
(RF amplifier) and leaves the A2 card.
(6) Power Control Input
The power control input (PC) comes from the A1 card. When the PC
input is H, Q207 and Q208 are in conduction, and +5VS power is
supplied to 422-MHz oscillator block (X203 to IC212) and also to
VR202. In this condition, the A2 card operates correctly.
When PC input becomes L, the 422-MHz oscillator block stops
oscillation and FL209 stops the 59.75-MHz RF video signal. VR202
also sets the final RF video output to the minimum level.
Page 14.04
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Matsushita Avionics Systems Corporation
COMPONENT MAINTENANCE MANUAL
PART NUMBER RD-AA5002 SERIES
23-32-47
E. RF Power Card Assembly (A3)
(1) The inputs to the A3 card come from the A5 card. They are as
follows:
· RF CH1-3 (combined RF video from modulator channels 1 thru 3)
· RF CH4-6 (combined RF video from modulator channels 4 thru 6)
· RF CH7-9 (combined RF video from modulator channels 7 thru 9)
· RF CH10-12 (combined RF video from modulator channels 10 thru 12)
A3CB301 (power divider/combiner) combines these inputs into one RF
video signal.
(2) The RF video signal from A3CB301 goes to A3IC301 (CATV amplifier).
A3IC301 is for CATV line extension, and has a bandwidth of 40 thru
450 MHz and a power gain of 38 dB as typical.
(3) The output of A3IC301 goes to A3CB301 (power divider/combiner),
which divides the RF video signal into four equal outputs. These
outputs connect to the middle plug of the J1 connector.
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Feb 20/2002
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COMPONENT MAINTENANCE MANUAL Video Modulator Unit (VMU)(21)
