-
LRU STATUS (green): indicates that no faults are detected during the self test of the ADF receiver.
-CONTROL FAIL (red): indicates that an ARINC input data is
faulty. The back is equipped with one ARINC 600 size one connector which includes three plugs:
-Top Plug (TP): connection with the automatic test circuit
-Middle Plug (MP): connection with the antenna and peripheral circuits
-Bottom Plug (BP): connection with the power supply circuit. Index pin code is 05.
**ON A/C 052-052,
A. ADF Receiver
(1)
External description (Ref. Fig. 005B) The face of the receiver is fitted with a handle, one attaching part, a TEST pushbutton switch and three LEDs. The name, color and function of the three LEDs are as follows:
-CONTROL INPUT/FAIL (red) indicates that the receiver is not receiving any information at the input ports, during self-test
-
LRU STATUS/PASS (green) indicates that no faults are detected during the self-test sequence
-
LRU STATUS/FAIL (red) indicates that a fault is detected during the
self-test sequence. The back of the ADF receiver contains an ARINC 600, shell size connector to provide electrical connections to the aircraft wiring via mount. Contact grouping is as follows :
-Top contact set - ATE interface
-Center contact set - System interconnections
-Bottom contact set - Power supply and bonding
(2)
Not Applicable
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R ADF - Receiver
R Figure 005B
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(3) Internal description (Ref. Fig. 006) The ADF receiver includes:
-an RF module,
-
a main processor assembly,
-
a power supply assembly,
-
a rear interconnect module,
-
a front panel display module,
-
a memory card interface module.
(a)
RF module The RF module contains receiver and synthesizer circuits to amplify and connvert the antenna derived sense, sine and cosine signals to baseband signals for digital signal processing. The RF receiver receives three signals from the combined sense/loop antenna, sense signal from the sense portion of the antenna and sine and cosine signals from the two bar-loops. The sense signal is coupled to a buffer amplifier that provides +4 to +6 dB gain and improves the voltage to noise figure of the receiver. The buffer amplifier also prevents loop modulation backward towards to sense antenna. The sense signal is summed in quadrature with the 105 Hz phase modulated sine and cosine signals. This composite signal is then upconverted to 10.7 MHz where a cristal filter provides selectivity. The signal is then amplified and detected for processing by the digital signal processor. The synthesiser provides local oscillator injection to upconvert the ADF RF signals to 10.7 MHz. The upconverted signal is passed through an IF filter and an IF amplifier. The signal is then down converted to 140 kHz. The 140 kHz IF signal is then amplified and sampled by the Analog/Didital (A/D) and sent to the DSP via the FIFO. Tuning (band switching) is accomplished by utilizing a 7 - band RF filter in conjunction with a band switching circuit. Essentially the tuning range of the ADF receiver is separated into seven discrete bands.
(b)
Main Processor Module The Main Processor Board serves as the heart of the ADF reciver. The analog signals from the RF module are processed and used to generate the ADF audio and bearing outputs. All aircraft interfaces are controlled by this board. All information on the front panel display is provided by this board. The board includes three major sections:
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ADF Receiver - Simplified Block Diagram
Figure 006
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-DSP section,
-DP (microprocessor) section,
-I/O section.
1 DSP section
_ The DSP section is used to process the analog outputs from the RF Module and to generate automatic gain control and other receiver commands as well as test signals to the RF Module. The DSP performs the bearing computations, Automatic Gain Control (AGC), Audio Filtering, Morse Code Tone detection, part of the BITE monitoring and RF module control. The DSP programs the synthesizer using the data from the DP. The composite ADF signal from the RF Module is digitized using an A/D converter. The A/D converter is also used to monitor signals from the BITE test points on the power supply voltages. The digitized data from the A/D converter is stored in a FIFO which is accessed by the DSP. Programmable Logic Devices (PLD) are used by the DSP to generate the control signals for the ADF frequency synthesizer. A Digital/Analog (D/A) converter generates the AGC and test control signals for the RF Module. A second D/A converter generates the audio outputs which are amplified to provide up to 50mW into a load ranging from 200 Ohms to 600 Ohms. A D/A converter generates the AGC, lateral and longitudinal modulations as well as the Audio signal. Data is exchanged with the CPU Section through a dual-port RAM, providing maximum throughput of both processors. The DSP provides the DP with the ADF bearing outputs periodically (every 50 ms) via the shared memory interface. The Main DSP also provides morse code report via the shared memory interface. In addition the DSP provides the audio outputs via the D/A.
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