-64/128 words/sec, 12 bit each 1 status line, a discrete output to send the FDIU status via SDAC to the CFDS 1 asynchronous output for test purposes in RS 232 characteristic
R 1EFF : 001-049, 051-099, 101-149, 151-199, 1 31-33-00Page 54 1201-299, 401-499, 1Aug 01/05 1 1 1CES 1 1 audio output for time synchronization of DFDR and Cockpit Voice Recorder (CVR)
**ON A/C 301-399,
(3) Output Characteristics
1 DITS-ARINC 429 output port (High speed)
1 DITS-ARINC 429 output port (Low speed)
1 DFDR bus, harvard biphase code
-
256 words/sec.
1 QAR bus, RZ code (optional)
-
256 words/sec. 1 status line, a discrete output to send the FDIU-part status via SDAC to the CFDS 1 asynchronous output for test purposes in RS 232 characteristic 1 audio output for time synchronization of DFDR and Cockpit Voice Recorder (CVR).
**ON A/C 001-049, 051-099, 101-105, 151-158, 201-209,
Post SB 31-1154 For A/C 151-154,201-207,
(3) Output Characteristics
1 DITS-ARINC 429 output port (Low speed)
1 DFDR bus, harvard biphase code
-
64/128 words/sec, 12 bit each
1 QAR bus, RZ code
-
64/128 words/sec., 12 bit each RS 232 characteristic 1 status line, a discrete output to send the FDIU status via SDAC to the CFDS 1 asynchronous output for test purposes in RS 232 characteristic 1 audio output for time synchronization of DFDR and Cockpit Voice Recorder (CVR)
R **ON A/C 106-149, 211-299, 301-399, 401-499,
(4) FDIMU (FDIU-Part) Functions The software controlled functions of the FDIMU (FDIU-part) are as given below:
-Collect and format various critical flight parameters and supply the DFDR with data for recording.
-
Supply a QAR (if installed) via a separate output with the same data frame as the DFDR.
-
Supply a PCMCIA media with the same data frame as the DFDR.
1EFF : ALL 1 31-33-00Page 55 1 1 Aug 01/05 1 1 1CES 1
-Supply an audio output, which is encoded with the GMT times to the CVR.
-Do an integrity check for the acceleration parameter for each flight.
-
Communicate with the CFDS for maintenance.
-
Communicate via a test connector with portable test equipment. The processor circuitry of the FDIMU is supplied with discrete and ARINC 429 parameters. The inputs are protected against overvoltage and wiring inversion. The processor circuits also filter, amplify, isolate and convert the input signals. The discrete input data are mutiplexed (1 receiver) and the status of these signals is stored and updated in the memory. The discrete output data is available through the output interface. These signals are output in case of initialisation and if an output status must change. The received ARINC 429 parameters are multiplexed and stored in the respective memory, controlled by input port, label and SDI. The ARINC 429 transmitter sends the BITE data from the DFDRS to the CFDIU. The recorder data for the DFDR and QAR (if installed) are generated by the microprocessor and output through the harvard biphase related bipolar RZ interface. The time reference for the Cockpit Voice Recorder (CVR) through the AMU is generated and synchronized by the DFDR and output as an audio signal (frequency shift 4193 Hz = logic 0, 3607 Hz = logic 1). The microprocessor generates the output formats for the DFDR/QAR and controls the RS 232 interface. The processor updates the data frames according to the received parameters. The whole data processing and interface control is managed on the processor board and the I/O board assembly. For the functions of the DMU-part refer to ATA 31-36-00 (Ref. 31-36-00)
**ON A/C 151-154, 159-199, 201-207, 210-210,
(4) FDIU Functions The software controlled functions of the FDIU are as given below:
-discrete parameter selection,
-selection of parameters from ARINC 429 buses,
-formatting of DFDR data output,
-processing of DFDR playback,
-Built-In Test Equipment (BITE),
-serving the RS 232 tester interface.
-DFDR-CVR synchronization The processor circuitry is supplied with discrete and ARINC 429 parameters. The inputs are protected against overvoltage and wiring
R 1EFF : 106-149, 151-154, 159-199, 201-207, 1 31-33-00Page 56 1210-299, 301-399, 401-499, 1Aug 01/05 1 1 1CES 1
R inversion. The processor circuits also filter, amplify, isolate and
R convert the input signals.
R The discrete input data are mutiplexed (1 receiver) and the status of
R these signals is stored and updated in the memory. The discrete
R output data is available through the output interface. These signals
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