Table 2 - FDIU Summary of Discrete Outputs
+------------------------------------------------------------------+ | FDIU BUS INPUTS | |------------------------------------------------------------------| | Connector | PIN | Speed | Source | Port | | | HI | LO | HI | LO | | No | |-----------|-----|------------------------------------------------|
| TP | 5A | 5B | X | | FWC 1 | 1 |
| MP | 5A | 5B | X | | FWC 2 | 2 |
| MP | 7J | 7K | | X | CLOCK | 3 |
| TP | 7J | 7K | | | SPARE | 4 |
| MP | 6A | 6B | | | SPARE | 5 |
| MP | 9E | 9F | | X | CFDS | 6 |
| MP | 8A | 8B | | X | FCDC2 | 7 |
| TP | 8A | 8B | | X | FCDC1 | 8 |
| MP | 8E | 8F | | | SPARE | 9 |
| TP | 7A | 7B | X | | SDAC 1 | 10 |
| MP | 7A | 7B | X | | SDAC 2 | 11 |
| TP | 7E | 7F | X | | DMC 1 | 12 |
| MP | 7E | 7F | X | | DMC 2 | 13 |
| TP | 8E | 8F | | | SPARE | 14 |
| MP | 8J | 8K | | X | BSCU2 | 15 |
| TP | 8J | 8K | | X | BSCU1 | 16 |
| TP | 9E | 9F | | | DFDR-REPLAY | |
| | | | | |(HAV.-BI-PHASE)| |
+------------------------------------------------------------------+ Table 3 - FDIU Summary of Bus Inputs
R 1EFF : 001-049, 051-099, 101-105, 151-199, 1 31-33-00Page 37 1201-210, 1May 01/05 1 1 1CES 1 +------------------------------------------------------------------+ | FDIU BUS OUTPUTS | |------------------------------------------------------------------| | Connector | PIN | Speed | Source | Remarks | | | HI | LO | HI | LO | | | |-----------|-----|------------------------------------------------| | MP | 9J | 9K | | X | CFDIU | ARINC 429 | | TP | 9A | 9B | | | QAR | RZ- CODE | | TP | 15A | 15B | | | CVR | AUDIO OUTPUT | | TP | 9J | 9K | | | DFDR | HAVARD-Bi-PHASE| +------------------------------------------------------------------+
Table 4 - FDIU Summary of Bus Outputs
R **ON A/C 106-149, 211-299, 301-399, 401-499,
C. FDIMU (FDIU-Part) Input/Output Pin Assignment (Ref. Fig. 007A) The connection between the related computers and the FDIMU (FDIU-part) is shown in the DFDRS inputs schematic. The summary of the input and output pin assignment is shown in:
-
Table 1 for the discrete inputs
-
Table 2 for the discrete outputs
-
Table 3 for the bus inputs
-
Table 4 for the bus outputs.
For the power supply, the test connector and the digital ground pin
assignment refer to ATA 31-36-00 (Ref. 31-36-00).
1EFF : ALL 1 31-33-00Page 38 1 1 Aug 01/05 1 1 1CES 1
DFDRS - Input Schematic
Figure 007A
R 1EFF : 106-149, 211-299, 301-399, 401-499, 1 31-33-00Page 39 1 1 Aug 01/05 1 1 1CES 1 +------------------------------------------------------------------+ | FDIMU (FDIU-Part) DISCRETE INPUTS | |------------------------------------------------------------------| | Connector | Pin | Explanation | |-----------|-----|------------------------------------------------| | MP | 11E | DFDR BITE | | | | | | MP | 11F | QAR Fail (if installed) | | | | | | MP | 11G | QAR Tape Low | | | | | | MP | 11H | Event Marker | | | | | | TP | 14F | MDDU Select | |------------------------------------------------------------------| | PROGRAM PINS | |------------------------------------------------------------------|
| | | |
| TP | 7G | Program Common |
| | | |
| TP | 7E | Program Ident MSB |
| TP | 7F | Program Ident LSB |
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