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6) The captain's clock provides GMT signals.
(3) Digital Flight Data Acquisition Management Unit Function
(a)
The DFDAMU receives 115v ac power from the FLIGHT RECORDER AC circuit breaker through either the manual or automatic switching circuits. The DFDAMU contains a switching regulator power supply that generates the necessary internal voltages and provides excitation outputs as follows: 1) 28v dc for accelerometer excitation 2) 5v dc for potentiometer sensor excitation 3) Constant current sources for temperature probe excitation.
(b)
The DFDAMU receives the flight parameters to be recorded. It processes and formats the signals. It then transmits the date to the DFDR for recording. Data acquisition, signal processing and output data streams are controlled by the central processing unit (CPU).
(c)
Each analog input signal is fed into an isolation network that adjusts the input level. A CPU controlled multiplexer selects one channel at a time for signal processing when it is required for output to the DFDR. The selected input signal then passes through a CPU controlled conditioner that demodulates and scales the signal prior to A/D conversion. The A/D network converts the signal into a 12 bit binary word for further processing by the CPU. Calibration of the analog interface is accomplished automatically by processing a known simulated input signal and revising the signal conditioner gain and offset constants as necessary.
(d)
Each discrete input enters the DFDAMU through a buffer network. When this signal is required for output to the DFDR, it is selected by the CPU controlled multiplexer. The selected input signal then passes through a comparator that threshold compares the signal against a logical 1 and logical 0 criteria. The signal is next converted to CPU compatible levels for further processing.
(e)
Each digital information transfer system (DITS) input signal enters by a pair of differential comparators that encode the data in a format suitable for processing. The channels are then selected by a multiplexer which is controlled by the DITS channel sequencer.
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(f)
The digital information transfer system (DITS) input signals are coded in ARINC 429 digital data format and are received either at low or high speed. Four of the DITS input channels have the capability to accept either high or low speed ARINC 429 data while the rest of the channels accept only low speed data. Each DITS input signal enters by a pair of differential comparators that encode the data in a format suitable for processing. The channels are then selected by a multiplexer which is controlled by a DITS channel sequencer. The label is read from the incoming data word to identify whether or not the data is stored in the DITS data RAM in a specific location based on input port and label. The CPU then samples the appropriate location in the DITS data RAM to obtain parameter data for output.
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本文链接地址：757 AMM 飞机维护手册 仪表 CHAPTER 31 - INSTRUMENTS 1(50)
