-
the software conditions of the AP function
-
the status of the GUIDANCE logic (monitoring of peripherals, FMGC hardware, watchdog)
-
the status of the long power failure from the power supply unit
-
the activation of the AP pushbutton switch on the FCU.
2 A/THR engage logic
_ The operation is similar to that of the AP engage logic.
3 FD engage logic
_
Engagement of the FD function depends on:
-
the software conditions of the AP function
-
the status of the GUIDANCE logic
-
the activation of the FD pushbutton switch.
4 FCU monitoring
_ This monitoring consists in reading, on the FCU bus, the data transmitted by the FMGC through the bus A. If an unhealthy operation is detected, the FCU FAIL signal is set to FAIL and causes the internal reconfiguration of the FCU between FCU 1 and FCU 2.
(3) Power supply unit (Ref. Fig. 005) The power supply unit delivers these voltages for the command channel: - +5 V BATT from a battery which keeps the FM common memory supplied - +15 V, -15 V, +5 V, +28 V from the filtered aircraft 28 V (Ref.
22-84-00).
These voltages are monitored by the program which takes into
account their status.
A circuit monitors the level of the 28 V and detects any power
cutoff.
Three cases may arise:
-Cutoffs less than 2 ms : these cutoffs have no impact on the operation of the FMGC.
-Short cutoffs : between 2 ms and 200 ms for the GUIDANCE part and between 2 ms and 4 s for the MANAGEMENT part. The detection circuits provide the safeguard of the RAM memories and enable the microprocessors to restart at power restoration. This transient must not cause disconnection of the AP, FD or A/THR systems
-Long cutoffs : more than 200 ms for the GUIDANCE part or 4 s for
the MANAGEMENT part. All these cutoffs result in disconnection of the AP, FD and A/THR systems. However, the microprocessors must be able to restart at power restoration. No flight data must be lost if the cutoff is less than 5 min.
B. Monitoring Channel (Guidance Only) This channel includes a digital part and a hardwired logic as the GUIDANCE COMMAND channel.
(1) Digital part
This part is integrated on two boards:
-a CPU AFS board
-an EXTENSION MON board
A memory module is located on the CPU AFS board.
It ensures these functions:
-ARINC acquisition of GUIDANCE peripherals
-
computation of the operational logic
-
computation of the AP/FD outer loop signals for the monitored modes
-
computation of the inner loops control laws and vote of the AP signals between the command and monitoring channels.
-transmission of computed data to the command channel through a low-speed ARINC bus called INTERNAL bus
-monitoring of the AP/FD signals through comparison with the command signals
FMGC - Architecture
Figure 004A
Power Supply Unit Figure 005
R 1EFF : 1 1 1CES ALL 1 111 22-83-00 Page 13 May 01/05
-monitoring of the alpha floor detection.
(2)
Hardwired logic It is identical with the logic of the command channel although it does not include the FCU monitoring circuits.
(3)
Power supply unit It is identical with the power supply unit of the command channel although it does not include a 5 V battery.
C. Back Connector
(Ref. Fig. 006)
The back of the computer is equipped with a size 3 connector.
D. Carry on Loader The wiring necessary to the loading of each FMGC by the carry on loader is routed from the FMGC back connectors to two identical connectors. These connectors 4CA1 and 4CA2 (one per computer) are located in the cockpit on the FMS LOAD panel 52VU.
R **ON A/C 062-099, 151-199, 201-212,
A. Command Channel
(Ref. Fig. 004)
(1) Flight management This digital section comprises three processors, each one being located on one board.
(a)
Input/output processor (input/output board) It ensures the functions below:
-ARINC interface with specific peripherals (MCDUs, data loader, EFIS, FMS Intersystem bus, printer/ACARS).
-dialogue with the other two processors through a common memory located on the same board.
(b)
Data base processor (data base board) The data bank is located on the same board in the mass memory. This board includes a memory module. This processor manages the data bank and certain background tasks which are not performed by the main processor. It dialogues with the other two processors through the common memory and with the FG part through a shared memory located on the board. The common memory is supplied with 5V from a battery.
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