(3)
Selection of TURB requires only the pitch channel to be engaged. The TURB position trips the mode select switch back to MAN if VOR/LOC and a localizer frequency is selected, or if AUTO APP is selected. With TURB selected, pitch channel control signals are reduced approximately 50%. If the roll channel is engaged, the roll command bank angle is limited to 8 degrees. Control wheel steering can be used; however, airplane response is reduced approximately 50%.
9. Yaw Damper Operation (All except coupler P/N 4084042)(Fig. 22)
NOTE: For aircraft with coupler P/N 4084042 installed (incorporating SB 27A1206), see 22-12-01.
A. The BITE system simultaneously checks the overall operation of each electronic unit and its interface with other components. Each series of tests can be completed in spite of individual test failures.
B. The BITE portion utilizes both analog and digital circuitry to test a high percentage of the computation and logic circuits. Manually initiated automatic go/no go testing checks dynamic circuits for gain and frequency and mode sensors for proper threshold levels. Each test is initiated with a single push button switch and evaluated by one of two colored indicators. These PASS and FAIL indicators provide the test status of each test without requiring any meter movement interpretation.
C. Prior to self-testing, a preliminary cockpit setup and a check of the BITE system are completed. Upon completion, self-testing may begin.
D. Typical BITE Control
(1)
The BITE provides a check of a majority of the signal computation circuitry. This is accomplished by comparing a programmed (pre-determined and scaled) signal with a fixed reference signal. Tolerance and polarity of each signal is also checked.
(2)
The BITE controls are on the front panel of the yaw damper coupler. At the top center of the panel is the test number window which indicates the specific test being computed. Below, is a row of two colored indicators which illuminate to indicate the status of the particular test shown in the test window. The left indicator is green to indicate a PASS condition; the right indicator is red to indicate FAIL condition. Directly below the PASS light is the GO switch used to trigger the sequence of tests. Directly below the FAIL light is the LAMP TEST switch used to check the PASS-FAIL lamps as well as the seven-segment display indicators behind the test number window. At the bottom of the panel, directly below the test number window, is the BITE (OFF-ARM) switch. The ARM position supplies BITE voltages to the multiplexer (MUX), comparator, and card input stimuli, and prepares circuits within the unit for testing (initializes the unit).
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E. Operation
(1)
Selecting BITE-ARM applies + 10 volts dc to the MUX, comparator, and card input stimuli circuits, and 5 volts dc to the integrated circuits. With these voltages applied, a power reset and power reset removal initializes the unit during test 0. The power reset: resets the 14 stage counter to zero; time complete not logic starts the clock; the sequence counter is cleared to 0; the FAIL latch is reset to PASS; and a PASS signal is injected into the MUX channel and the comparator. The power reset removal: removes the reset from the 14 stage counter and starts a .64 second pulse; removes the clear from the sequence counter; and removes the reset from the FAIL latch. With time completed for test 0: the 14 stage counter stops and the injected comparator signal (PASS) causes the PASS output to the latch to illuminate the PASS indicator. This output is fed back to prevent a fail light at a later time. This terminates test 0.
(2)
To check the PASS-FAIL lamps and the seven-segment digital display, the LAMP TEST switch is pushed and held. Pressing the switch injects a fail signal into the MUX and comparator; the pass light feed back path is opened, allowing a comparator fail signal to trip the fail latch; the FAIL indicator illuminates; and 8 appears at the test number window as long as the switch remains pressed.
(3)
To select the next test, the GO switch is pressed and released. This action triggers a pulse which: resets the 14 stage counter and the FAIL latch; increments the sequence counter; and repeats power reset and power reset removal action as stated previously, except the sequence counter is not cleared and the memory outputs inject the proper stimuli for the particular test. When the GO switch is pressed after the last test, a dedicated memory output simulates a power reset back to test 0.
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519 Typical BITE Block Diagram
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