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MMR - External Description
Figure 004A
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R MMR - Block Diagram
R Figure 005
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R The aircraft supplies the 115 VAC, 400 Hz, single phase power to
R the MMR. The input power is routed from the rear interconnect to
R the forward power supply. The forward power supply provides power
R factor corrections, and outputs +200 VDC for the aft power supply.
R The aft power supply steps the +200 VDC down to +/- 6.5 and +/-
R 13.5 VDC outputs. These unregulated voltages are routed to the
R other subassemblies where they are post-regulated to +/- 5 VDC and
R +/- 12 VDC. Post-regulation provides a level of separation between
R the subassemblies and possible noise on the power lines. It will
R also allow shut-off of the circuit areas when not needed for a
R specific phase of flight (not used today).
R
R - ILS Receiver
R The MMR receives VHF localizer and UHF glideslope signals at the
R antenna jacks in the bottom plug of the rear connector. Coaxial
R cables route the RF from the rear connector to the ILS receiver.
R The ILS receiver includes four functional areas: VHF receiver, UHF
R receiver, primary instrumentation processor, and monitor
R instrumentation processor.
R
R The VHF receiver filters, mixes and amplifies VHF signals. The
R resulting intermediate frequency signals are converted into serial
R data and processed by both the primary and the monitor
R instrumentation circuits. The UHF receiver filters, mixes,
R amplifies, and detects UHF signals. The detected signals are
R converted into serial data and processed by the instrumentation
R processors. The primary instrumentation processor outputs flight
R path deviations to the system processor. The system processor
R forwards the flight path deviations to the aircraft instrumentation
R and auto-pilot computers (FMGC).
R The monitor instrumentation processor performs a validity check of
R the primary instrumentation processor deviation output, and
R disables the outputs if the check fails. The primary and monitor
R instrumentation processors use ARINC 429 buses for
R intercommunications and for communications with the system
R processor.
R
R - GPS Receiver
R The MMR receives RF signals through an active GPS antenna
R (preamplifier implemented within the antenna). The GPS receiver
R filters, mixes, and performs analog-to-digital conversions. The
R resulting data is processed by microprocessors that output
R position, velocity, time, and integrity data to the system
R processor. The system processor transmits ARINC 743A-compliant data
R for use by other aircraft systems. The GPS receiver also outputs a
R time mark discrete signal that tells users of the ARINC 743A data
R the instant in time when the position solution is valid.
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-System Processor The system processor controls the flow of data to the ILS and GPS receivers including mode and frequency selections, GPS initialization, and maintenance data requests. The system processor also controls the transmission of output data including ILS deviation, GPS position, velocity, time, integrity, time marks and maintenance data. Circuitry on the system processor converts received data from serial into parallel and also formats parallel data to serial data for transmission on the bus.
R **ON A/C 001-049, 101-149, 151-199, 201-299, 301-399, 401-499,
A. MMR
(1)
External description (Ref. Fig. 004A) The face of the MMR is fitted with a handle, two attaching parts, a TEST pushbutton switch and four Light Emitting Diodes (LEDs). The four LEDs have the following name, color and function:
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