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时间:2011-09-29 14:31来源:蓝天飞行翻译 作者:航空
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 (4)  
Inside the case, two separate and independent channels of on-line electronics eliminate single point failure. The dual channels increase overall reliability of the FQIS. Each channel consists of four card assemblies interconnected through a mother board, plus independent power supply cards. The cards are as follows:

 (a)  
Excitation card assembly provides signals to the tank units, and compensators.

 (b)  
Null/balance card assembly receives and digitizes the signals from the tank units and compensators.

 (c)  
Digital I/O card digitizes analog inputs, and acts as an interface between the FQPU and FQIS components.

 (d)  
Central processing unit (CPU) card assembly makes all computations for the FQIS.

 (5)  
The FQPU receives signals from the tanks units, compensators, densitometers, load select control, and air/ground relay, and does computations as programmed. Output signals of fuel quantity go to the fuel quantity indicator, and the load select indicators. A signal is also sent to the EICAS computers and FUEL CONFIG light on P5, warning of low fuel, fuel imbalance, or system faults. Fueling valve control signals are available during the fueling operation. The FQPU also supplies failure monitoring, and built-in-test.

 (6)  
Channels

 (a)  
The FQPU has two channels that independently receives fuel measurement data, calculates the fuel quantity, and produces the digital output data for possible transmission.


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 28-41-00
 ú CONFIG ú 08 Page 18 ú Sep 20/95

A

757
MAINTENANCE MANUAL

FQIS PROCESSOR E3-4
SEE ARACK
MAIN EQUIPMENT CENTER
POWER SUPPLY
CHANNEL 1
NO. 1
CHANNEL 2 POWER SUPPLY NO. 2
T-HOOK
FQIS PROCESSOR
A
FQIS Processor Figure 10
PRESS TEST SWITCH
FQIS PROCESSOR DISPLAY
DISPLAY CHANNEL SELECT SWITCH
RESET SWITCH
VERIFY SWITCH
BIT SWITCH
T-HOOK
FRONT HOLD-DOWN EXTRACTORS
EFFECTIVITYùùùùùùùùùùùùùùùùùùùùùùùùùùùùùù. GUN 001-010 ú

 28-41-00
 ú CONFIG ú 02 Page 19 ú Jun 20/91

 (7)

A

757
MAINTENANCE MANUAL

 (b)  
The two channels are completely redundant in order to prevent a single point failure from disabling the FQPU.
 
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