(2)
The do discrete signals, such as air data valid and air conditioning switches, are input into the discrete signal conditioners. There the signals are level shifted to a 5V TTL level output and applied to the digital I/O.
B. The digital inputs arrive at the PDC in a variety of forms from the CDU, Omega Navigation System, automatic flight control system, and DME.
(1)
The DME interface contains a binary counter operating from a 4-MHz clock. The circuit accepts one of two pulse pair input signals and measures the time interval between them. The counter digital time interval data is shifted into a serial register, and clocked into the digital I/O circuit.
(2)
The CDU sends data to the PDC from its keyboard function generator. Switch information from the CDU front panel and wraparound data from the symbol generator are sent to the digital I/O circuit in the PDC through a 4-MHz clocked serial digital data bus.
(3)
On GJ B-2509 and B-2510 The digital input from the AFCS mode control panel is a serial data bus applied in the PDC ARINC 429 receiver. The 32-bit word is stored in two 16-bit serial buffers and clocked into the digital I/O circuits.
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10. Functional Description - Processing (Fig. 3)
A. The processing circuits of the PDC include the digital I/O - digital interface, the central processing unit (CPU) and memory.
(1)
The digital I/O and digital interface circuits provide all interfacing between the CPU and external systems. The digital I/O circuits consist of a real time clock, several parallel and serial registers, parallel-to-serial converter, data buffers, registers and analog control logic. The digital I/O circuits send interrupt signals to the CPU as a notification of incoming data or system status, and store the data in registers until the CPU is ready to receive. The real time clock sends an interrupt to the CPU as a notification that data transmission is complete.
(2)
The central processor unit (CPU) executes the PDC instruction set through a microprogram stored in semiconductor programmable read-only memory (PROM). The instruction set includes the operational flight program and interrupt routines. The flight program computes performance targets and data from system input and evaluates it with respect to the programmed capability of the engines. The interrupt routines consist of data entry routines, which control the digital I/O circuits, a power initialization routine, power down warning routine, and a self-test routine. The interrupt routines are prioritized, with the power initialization receiving highest priority and self-test the lowest.
(3)
The memory contains programmable read-only memory (PROM) with both instructions and fixed data used to guide and sequence the computer. A random access memory (RAM) scratch pad memory stores intermediate results of computations, and acts as a buffer for input/output data. The protected memory contains a scratch pad to store input data which must be saved during short power outage intervals.
11. Functional Description - Output (Fig. 2 and 3)
A. The analog outputs from the PDC are generated in the digital-to-analog converter, then sent to either the multiplexer or regulator. The A/D converter uses a ramp generator and comparator to generate a dc output corresponding to a digital input for the digital I/O circuits. In the regulator the dc signals are applied to holding capacitors, which are periodically updated, to provide the dc outputs to EPR and Mach/Airspeed indicators.
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B. The digital outputs include the CDU interface and the mode annunciator interface.
(1)
The CDU output signal is a 20-kHz clocked 128-bit digital word sent from the digital I/O circuits. The data sent includes control words, which determine character position on the CRT, and data words, which determine the character displayed.
(2)
The mode annunciator driver decodes three discrete signals from the digital I/O circuits to provide a one-of-eight active output (one for each flight mode) to the mode annunciator. There is also an independent discrete output for the TURB mode.
(3)
The ARINC 429 transmitter contains a 32-bit serial data buffer register that outputs its contents sequentially to the AFCS.
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