757 AMM 飞机维护手册 自动飞行 AUTOFLIGHT 1(97)

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 5)  The autoland bus isolation logic maintains the center AFDS on battery power for the duration of the approach unless reset by one of the following conditions: a) A failure is detected which reduces the system
 redundancy level to less than the fail operational
 configuration. b) Total autopilot disconnect. c) Go-around has been initiated and the airplane is at an
 altitude of 100 feet or more.
 6)  Except for total autopilot disconnect, center bus isolation is latched when: a) The airplane is below alert height and not in the G/A
 mode.
 b)  The airplane is below 100 feet and in G/A mode.
 c)  Center bus isolation was reset previously due to
 reduced system redundancy.
 (2) AFDS FCC Operation
 (a) FCC Functional Partitioning (Fig. 6)
 1)  The FCC is divided into two separate sections; one section is controlled by the CAPS processor and the other section is controlled by the Input/Output (I/O) controller. The section under the I/O controller provides input buffering, signal conversion, and storage of analog, digital, and discrete signals received from external sensors and control switches. The section under the CAPS processor uses the CAPS transfer bus to provide processor related functions such as memory access, computation of analog servo commands, processing of discrete input information, monitoring functions, and processing of cross channel receiver information. The CAPS processor section also contains and implements the primary application program for the FCC.
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MAINTENANCE MANUAL

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MAINTENANCE MANUAL

 2)  The link between the I/O controller section and the CAPS processor section is provided by the I/O buffer. Data words may be stored or retrieved by either the I/O controller or the CAPS processor, with the storage location based on the source and contents of the data word. The I/O buffer also contains three internally generated status bits for each parameter. The status bits are read by the processor in order to determine the status of the data.
ARINC 429 I/O
 1)  The ARINC 429 I/O assembly provides an interface between the internal I/O bus and the ARINC 429 input and output buses. The assembly handles seven ARINC 429 input buses from external sources, and transmits data to external units via three output buses. Three ARINC 429 input ports are also provided for FCC internal signal wraparound to facilitate built-in test requirements.
Digital Discrete Input
 1)  The digital discrete assembly provides an interface between the internal FCC I/O bus and discrete inputs. The assembly also receives one ARINC 429 input (from Internal Reference System (IRS) and provides three ARINC 429 inputs (to the MCP, Flight Data Acquisition Unit (FDAU), and EFIS). Data transfer is directed by the I/O controller.
Analog Input
 1)  The analog input assembly provides for the conversion of analog input signals into digital words for use in FCC mode control computations. Internal test voltages are monitored for software scaling and fault detection. Wraparound signals from pitch servo assembly and roll/yaw servo assembly are converted to digital words for use in software monitoring routines. The converted inputs are multiplexed onto the I/O data bus as two 8-bit words.
Roll/Yaw Servo
 1)  The roll/yaw servo assembly provides an interface between the CAPS processor and the aileron and rudder hydraulic servo valves. Servo commands from the CAPS processor are converted to analog signals and then summed with the present servo position signal to provide the drive for the airplane hydraulic servo valves.
Discrete/Warn I/O
 1)  The discrete/warn I/O assembly provides discrete-to-TTL level translation of +28 volt discrete signals for use by the FCC processors. The assembly also monitors the status of the autopilot servo engage signals, and provides warning outputs if a problem is detected.
　
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