Detent comparators verify that the aircraft control surfaces are following the commanded signals. Dual comparators, one in hardware and one in software, monitor the servo position and the aircraft control surface position. An incorrect comparison generates a fault signal for use in software.
(b)
Linear variable differential transducer (LVDT) signal outputs are checked by hardware monitors. The hardware monitors detect faults caused by shorted wires, broken wires, or loss of excitation, and generate a fault signal for use in software. These monitors are used for the servo position sensor inputs. Signal inputs from sensors other than LVDTs are monitored by software. Signal selection failure detection routines are used to determine sensor correctness and to provide voter outputs for multichannel operation. Incorrect sensor signals are voted out of the final results.
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(c) Discrete input and output interfaces are monitored by software which detects shorted wires. These monitors are used for the caution/warning inputs and outputs, engage and arm solenoid power, trim outputs, engage and arm commands and inputs, and autoland status annunciator inputs and outputs. The interface monitor circuits are tested, as appropriate, at power up or prior to engagement of autopilot/autoland.
The ARINC 429 inputs from system LRUs are checked in two ways. First, the FCC checks the sign status matrix to verify the validity of the incoming data. The buffer memory locations are also periodically tested to determine if the data words have been updated. If the words have not been updated, then a fault is assumed and the data words at the tested memory locations are not used.
The ARINC 429 test words are generated by the FCC. The test words are used to verify the correct operation of the circuitry involved in communication with the mode control panel and the other FCCs in the system. The test words are sent to the receiving system unit, operated on, and then transmitted back to the originating FCC. The results are compared with the expected answers to determine if faults exist.
(4) FCC Self Test
(a)
The FCC provides a number of self-tests. The tests are divided into two basic categories: power-up/pre-engage tests and operation verification tests. The power-up/pre-engage category includes tests which would cause adverse system reactions if performed during flight. The operation verification category provides critical function monitoring such as the CAPS processor memories, interfacing electronics, and power supplies. These types of functions are monitored on a continuous or recurring basis.
(b)
CAPS Processor
1) The CAPS processor self-test is implemented using several techniques, and provides checks of processor components and data, address, and control paths. During execution of the self-test program, the program monitor counts the number of microcycles in each iteration of the self-test program and also monitors the execution time of the program. A second hardware-implemented check is provided by the processor parity monitor. The parity monitor checks the instruction mapping into the microprogram memory. Both self-test program monitors are checked at power up.
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2) The computation rate of the processor is continuously checked during the normal operation of the FCC. During each 25 millisecond computation period, a software generated signal is sent to the program monitor. If the signal is more than |5 milliseconds out of tolerance, a fault signal is generated. The circuit does not reset until two consecutive within tolerance signals are received. The monitor circuit is checked at power up for correct fault response.
(c) Memories 1) The program memory is checked by a software routine. The checksum of the ROM contents is compared with the expected sum (stored in memory), and a fault signal is generated if the comparison fails.
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